Synopsys Synplify 2019.03 SP1

Synopsys Synplify is an industrial standard for creating high-performance FPGA designs and cost savings. Synplify software supports the latest VHDL and Verilog language structure including SystemVerilog and VHDL-2008. The software also supports FPGA architecture from many FPGA providers, including Altera, Achronix, Lattice, Microsemi and Xilinx, all from a RTL and bound source. The Synplify Pro software uses a single interface, which is easy to use and is capable of implementing an increased aggregation and an intuitive HDL code analysis.

Features of Synopsys Synplify

• Incremental, block-based and bottom-up flows for consistent results from one run to the next
• Automatic compile points incremental flow for up to 4x faster runtime while maintaining QoR
• Accelerated runtimes with support for up to 4 processors
• Scripting and Tcl/Find support for flow automation and customizable synthesis, debug and reporting
• Optimal area and timing results using FPGAs from Achronix, Altera, Lattice, Microsemi, Xilinx
• Hierarchical team design flow allowing parallel and/or geographically distributed design development
• Comprehensive language support including Verilog, VHDL, SystemVerilog, VHDL-2008 and mixed-language design
• FSM Compiler and FSM Explorer for automatic extraction and optimization of finite state machines from RTL
• Graphical state machine viewer to automatically create bubble diagrams for debugging and documenting FSMs
• Automatic memory and DSP inference provides automatic implementation of a design with optimal area, power and timing quality of results
• Incremental static timing for analysis allows updates to timing exception constraints with immediate visibility into results, without re-synthesis
• HDL Analyst interactive graphical analysis and debug tool for design diagnosis, problem isolation and functional and performance analysis.

System requirements:

• The operating system was supported: Windows 7/8/10
• Empty disk space: 2 GB or more.